A semiconductor chip is made up of an array of devices whose contacts are connected by patterns of metallic wiring. In very large-scale integrated (VLSI) circuit chips, the metallic wiring patterns are multi-layered, and separated by layers of insulating material. Interconnection between the different levels of metal wiring patterns is made by holes (or "via" holes), which are etched through the insulator layers. Chip designs usually consist of one or two wiring levels, but the use of three wiring levels is becoming much more prominent.
Because of circuit economics and performance requirements, the addition of more wiring levels usually cannot be accompanied by higher costs, even though additional processing steps are involved. As an example, many semiconductor processes require 15 or more mask levels to complete metallization. Thus, greater efficiency must be achieved in this area of interconnection, i.e., the Back End of the Line (BEOL), so that much higher VLSI densities can be achieved economically, without detracting from the overall performance of the chip.
The density of a particular device is often characterized in terms of its "pitch", which is defined as the area encompassing a via and the space next to a via extending to the next via. A "lower" or "minimum" pitch indicates a much tighter arrangement of vias and adjacent spaces, and is desirable because it permits a much higher density of features in the device. However, minimum pitch also makes the task of precise wiring and interconnection more difficult.
One technique that has been utilized for metallization in and between vias is often referred to as "lift-off". In this technique, a via is first tapered by etching, followed by the application of a photoresist, which is exposed in the area intended for metal deposition. After the photoresist is developed in desired areas, a metal like aluminum is evaporated into the vias. Lifting off the resist removes the overlying metal, thereby forming the desired stenciled pattern. The process can be repeated between successively deposited insulation layers when multiple levels of metallization for wiring patterns is desired.
While the lift-off technique was suitable for the metallization of many devices, its value was limited to some degree in higher density situations. Lift-off requires line-of-sight deposition and patterning of metal, i.e., in the evaporation process. For a device having a pitch of less than about 2.5 microns, line-of-sight deposition is often not practical, since the deposition source has to be too far away from the wafer, i.e., from the photoresist surface. Furthermore, the lift-off technique can result in an undesirable, rounded feature profile. The technique is also usually limited to temperatures below 200.degree. C.-300.degree. C., the point at which most photoresist materials begin to degrade.
An alternative to the lift-off technique is known as reactive ion etching (RIE). In this technique, a blanket layer of metal is applied over the contoured vias, followed by the application of a photoresist on top of the metal. The exposed and developed photoresist is then used as a mask, permitting the metal to be subtractively etched. Once the photoresist is stripped, the desired pattern is achieved. RIE allows for a tighter pitch, more directional sidewalls, and a desirable feature profile.
However, there are some disadvantages associated with the RIE-based technique, especially when a pitch as low as 2 to 3 microns is desired. In the case of aluminum metallization, alloying with copper is usually necessary to ensure electromigration resistance. However, aluminum-copper alloys are often difficult to etch using the RIE technique. Residual metal often remains, and is corroded by the etching solutions. This type of corrosion often leads to subsequent electrical shorting in the semiconductor chip.
A process developed to overcome some of the drawbacks of the lift-off and RIE-based techniques is sometimes referred to as the "damascene" process. An embodiment of this technology is described in U.S. Pat. No. 4,789,648 of M. Chow et al. The process relies in part on the use of overlapping masks to define vias and interconnection lines. In one embodiment, an insulation layer is applied over a layer of patterned conductive material, followed by the deposition of an etch stop material. Contact holes are photolithographically defined in the etch stop material. A second planarized insulation layer is then deposited, patterned, and etched down to the etch stop material to define desired wiring channels which will be in alignment with previously-formed contact holes in the etch stop material. In the locations where the contact holes are exposed, etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and vias etched into the second and first layers of insulation, respectively, are then over-filled with metallization. The excess metallization on the surface is removed by a suitable technique, such as chemical-mechanical polishing. The steps can be repeated for additional layers of metallization.
The damascene process results in a structure with a very tightly controlled pitch, e.g., up to about 0.75 micron. Furthermore, the structure is highly planarized, and is thus resistant to some of the problems associated with nonplanar structures, e.g., shorting due to thinning insulation between adjacent levels of metallization. Moreover, the fabrication process is simpler than that used previously, since patterned conductive lines are formed simultaneously with stud vias.
As the industry moves toward even denser semiconductor circuits, additional processing steps will be required, e.g., to make the pitch even tighter, or to construct higher levels of metallization and vias. These additional steps need to be streamlined to make the overall process as efficient as possible, in view of the competitive economic pressures discussed previously.
An example of an instance in which streamlined manufacturing has been successful is offered by the teaching of U.S. Pat. No. 4,962,058, issued to J. Cronin et al. The patent discloses an improved process for forming a multi-level metallization structure from a single layer of conductive material. The wiring structures described in Cronin et al. have external connections represented by stud-up and stud-down structures. The number of wire processing steps is decreased in that invention, as compared to prior art processes.
The Cronin et al. process involves the masking and etching of a planar insulating layer to form a plurality of wiring troughs in the upper portion of the insulating layer, and at least one stud-down via in a lower portion of the insulating layer, followed by the deposition of a layer of metal to fill the vias and the troughs, with excess metal residing on top of the structure. The metal surface is then masked and etched to define at least one stud-up, as well as a plurality of interconnection lines. (RIE is usually required, although such a technique in this particular instance may result in the presence of residual etch material and metal "stringers".) The masking/etching step is carried out in a manner which results in a desired level of stud-up structures being situated on top of the mask material and the layer of conductive material. Again, all of the stud-downs, stud-ups, and interconnection lines have been formed from the same layer of metal. The various stud-ups, e.g., as depicted in FIG. 4D of the patent, continue to reside above the surface of the top insulating layer. Additional processing steps may be employed to deposit additional insulating material so that these stud-ups are planarized to the surface of the overall structure.
It's clear from the foregoing, as well as from a survey of the state of the art, that many improvements have been made in the area of high density integrated circuits. However, even further improvement is necessary as the dimensions of these types of circuits become even smaller. Specifically, improved techniques are desirable for efficiently preparing semiconductor structures which include self-aligned stud-ups, stud-downs, and interconnection lines formed from a single layer of metal. The new techniques should streamline the fabrication process as much as possible, while still resulting in devices which have a very tight pitch. The devices should also be characterized by as small a number of defects as possible, e.g., minimal electrical shorts or "necking" effects. Moreover, the processes employed should allow for the formation of both thick and thin wiring structures, even in a multi-level structure, as well as allowing for the formation of studs of very precise dimensions.